In sensor technology, capacitive operating principles are being used ever more frequently. Examples of this are, in addition to the conventional field of humidity measurement, fill-level measurement by means of plate capacitor arrangements submerged in the medium, pressure measurement by means of membranes formed as a plate capacitor, or measurement of acceleration and rotation rates with the aid of micromechanical sensors. Advantages are the low power level, the simple design and the virtual freedom from wear.
Various methods are used for measuring capacitance. In modern systems, a digital output signal of the sensor module is fundamentally necessary. The conventional method of using the capacitance as a frequency-determining part of an oscillation-generating circuit to carry out a frequency-to-voltage conversion and then an analogue-to-digital conversion is one possibility. Other methods are based on impedance measurement or the evaluation of capacitive bridge circuits. In the latter method the bridge is stimulated with an alternating voltage and the output voltage after synchronous rectification is amplified and A/D converted. In all of these methods, a—usually very small—signal is converted into a digital signal in several steps. This is expensive, involves many error sources which are an obstacle to high precision requirements and, as a rule, is also slow. The fields of use named further above require ever shorter response times, which go down to the sub-ms range, in the sequence of their enumeration.
A generic converter and generic method which make a direct conversion of the capacitance into a digital signal possible and are very robust and easy to integrate are described in U.S. Pat. No. 5,990,578. The conversion method is based on a charge balance method.
The circuit arrangement in this respect is designed as a so-called charge balancing modulator (or CBM) and has an operational amplifier, between the output and inverting input of which an integration capacitor CI is switched. The non-inverting input of the operational amplifier is connected to a ground, which represents the referene potential. A precision capacitor CS and a reference capacitor CR are further provided. One electrode of the precision capacitor CS is connected via a first changeover switch to either a known reference potential VR or the ground. The other electrode of the precision capacitor is connected by means of a second changeover switch, at the same time as the first changeover switch, to the ground or the inverting input of the operational amplifier. One electrode of the reference capacitor CR is connected via a third changeover switch to either the reference potential VR or ground. The other electrode of the reference capacitor CR is connected by means of a fourth changeover switch, at the same time as the third changeover switch, to the ground or the inverting input.
A clocked comparator is connected at the output of the operational amplifier. The first and the second changeover switches are switched synchronously with the clock signal of a clock generator. The third and the fourth changeover switches are switched synchronously by the output of a gate circuit, wherein a switching signal is emitted when the comparator output signals that a threshold voltage has been exceeded.
In this way, the charge quantity VR*CS is transmitted in every clock pulse to the integration capacitor CI. The charge quantity changes when the threshold voltage of the comparator is exceeded at the output of the operational amplifier, whereby the comparator adopts another switch state at its output. Then, when a clocked pulse occurs, a switching pulse is triggered for the third and fourth changeover switches. As a result, every time that the threshold voltage is exceeded by the integration capacitor CI, a charge quantity VR*CR is additionally subtracted. When the threshold voltage is exceeded, the charge quantity VR*CS-VR*CR is transferred to the integration capacitor in every clock pulse. The output voltage of the operational amplifier thereby falls below the threshold voltage of the comparator, whereby the latter adopts its old state again, and the subtraction of the charge quantity ends. Then, charges VR*CS are again delivered to the integration capacitor CI in every clock pulse until a voltage which lies above the threshold voltage is reached again at the output of the operational amplifier. The process thus repeats itself.
During each discharge of the reference capacitor, a pulse is produced at the gate output. The number z of pulses, relative to the number n of clocked pulses, is a measure of the relationship of the capacitances CS and CR, as VR*(CS*n)=VR*(CR*z). z is thus a digital value for the analogue variable CS. As the method is to be counted among the integrating converter methods (one LSB step per clock period), the conversion time for 14 bit resolution (16,384 steps) in the case of capacitances of a few pF lies in the single-digit ms range, even if the circuit is integrated via modern CMOS processes.
Conversion methods which operate in a similar way are also described in WO 2006/008207 A1 and U.S. Pat. No. 6,970,126. There, a sigma-delta modulator is used instead of the charge-balancing modulator. The difference between these modulators is the return mechanism not present in the case of the sigma-delta modulator. No self-contained conversion of a particular resolution is thereby given; rather a continuous bit stream is emitted, which is converted by a digital filter into a result with a particular bit width and sampling rate. Although a higher sampling rate can thereby be achieved in some cases, when the capacitance changes suddenly the result with the final precision is reached only after several samples. The problem of the response time being too long is not solved by this.
U.S. Pat. No. 7,236,113 and U.S. Pat. No. 6,509,746 deal with correction and diagnosis methods when sigma-delta converters are used for capacitance measurement.